Data Sheet
ADP5042
Rev. A | Page 19 of 32
Thermal Protection
In the event that the junction temperature rises above 150癈,
the thermal shutdown circuit turns off the buck and the LDOs.
Extreme junction temperatures can be the result of high current
operation, poor circuit board design, or high ambient temperature.
A 20癈 hysteresis is included so that when thermal shutdown
occurs, the buck and LDOs do not return to operation until the
on-chip temperature drops below 130癈. When coming out of
thermal shutdown, soft start is initiated.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout
(UVLO) circuitry is integrated in the system. If the input
voltage on AVIN drops below a typical 2.15 V UVLO threshold,
all channels shut down. In the buck channel, both the power
switch and the synchronous rectifier turn off. When the voltage
on AVIN rises above the UVLO threshold, the part is enabled
once more.
Alternatively, the user can select device models with a UVLO
set at a higher level, suitable for 5 V applications. For these
models, the device hits the turn-off threshold when the input
supply drops to 3.65 V typical.
Enable/Shutdown
The ADP5042 has individual control pins for each regulator. A
logic level high applied to the ENx pin activates a regulator, a
logic level low turns off a regulator.
When regulators are turned off after a Watchdog 2 event (see
the Watchdog 2 Input section), the reactivation of the regulator
occurs with a factory programmed order (see Table 9). The
delay between the regulator activation (t
D1
, t
D2
) is 2 ms.
Table 9. ADP5042 Regulators Sequencing
REGSEQ[1:0] Regulators Sequence (First to Last)
0
0
LDO1 ?LDO2 ?Buck
0
1
Buck ?LDO1 ?LDO2
1
0
LDO1 ?Buck ?LDO2
1
1
No sequence, all regulators start at same time
BUCK SECTION
The buck uses a fixed frequency and high speed current mode
architecture. The buck operates with an input voltage of 2.3 V
to 5.5 V.
Control Scheme
The buck operates with a fixed frequency, current mode PWM
control architecture at medium to high loads for high efficiency
but shift to a power save mode (PSM) control scheme at light
loads to lower the regulation power losses. When operating in
fixed frequency PWM mode, the duty cycle of the integrated
switches is adjusted and regulates the output voltage. When
operating in PSM at light loads, the output voltage is controlled
in a hysteretic manner, with higher output voltage ripple. During
part of this time, the converter is able to stop switching and
enters an idle mode, which improves conversion efficiency.
PWM Mode
In PWM mode, the buck operates at a fixed frequency of 3 MHz,
set by an internal oscillator. At the start of each oscillator cycle,
the PFET switch is turned on, sending a positive voltage across
the inductor. Current in the inductor increases until the current
sense signal crosses the peak inductor current threshold that
turns off the PFET switch and turns on the NFET synchronous
rectifier. This sends a negative voltage across the inductor,
causing the inductor current to decrease. The synchronous
rectifier stays on for the rest of the cycle. The buck regulates the
output voltage by adjusting the peak inductor current threshold.
Power Save Mode (PSM)
The buck smoothly transitions to PSM operation when the load
current decreases below the PSM current threshold. When the
buck enters power save mode, an offset is induced in the PWM
regulation level, which makes the output voltage rise. When the
output voltage reaches a level that is approximately 1.5% above
the PWM regulation level, PWM operation is turned off. At this
point, both power switches are off, and the buck enters an idle
mode. The output capacitor discharges until the output voltage
falls to the PWM regulation voltage, at which point the device
drives the inductor to make the output voltage rise again to the
upper threshold. This process is repeated while the load current
is below the PSM current threshold.
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs
a scheme that enables this current to remain accurately con-
trolled, independent of input and output voltage levels. This
scheme also ensures that there is very little hysteresis between
the PSM current threshold for entry to and exit from the PSM.
The PSM current threshold is optimized for excellent efficiency
over all load currents.
Short-Circuit Protection
The buck includes frequency foldback to prevent output current
runaway on a hard short. When the voltage at the feedback pin
falls below half the target output voltage, indicating the possi-
bility of a hard short at the output, the switching frequency is
reduced to half the internal oscillator frequency. The reduction
in the switching frequency allows more time for the inductor to
discharge, preventing a runaway of output current.
Soft Start
The buck has an internal soft start function that ramps the
output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the converter.
Current Limit
The buck has protection circuitry to limit the amount of
positive current flowing through the PFET switch and the
amount of negative current flowing through the synchronous
rectifier. The positive current limit on the power switch limits
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